3D Nanostructured Silicon Relying on Hard Mask Engineering for High Temperature Annealing (HME-HTA) Processes for Electronic Devices

Bopp, M.Coronel, P.Judong, F.Jouannic, K.Talbot, A.Ristoiu, D.Pribat, C.Bardos, N.Pico, F.Samson, M. P.Dainesi, P.Ionescu, A. M.Skotnicki, T.2009-07-152009-07-152009-07-152008https://infoscience.epfl.ch/handle/20.500.14299/41322Annealing silicon at high temperatures in hydrogen ambiance has been reported to induce surface diffusion of silicon; in these conditions, adapted 2D arrays of trenches etched in Bulk Si are transformed into buried cavities creating suspended membranes. A 3D nanostructuration of silicon through hard mask engineering and high temperature annealing in hydrogen ambiance is reported. By using a nitride-oxide hard mask stack instead of a sacrificial oxide hard mask for a free surface (maskless) annealing, we open new technological and design possibilities using 2D arrays of various geometry trenches. Implications and potential device applications are discussed.silicon high temperature annealinghard maskburied cavityIndependant double gate transistor3D Nanostructured Silicon Relying on Hard Mask Engineering for High Temperature Annealing (HME-HTA) Processes for Electronic Devicestext::conference output::conference proceedings::conference paper