Balatsoukas Stimming, AlexiosPreyss, NicholasCevrero, AlessandroBurg, AndreasRoth, Christoph2013-06-022013-06-022013-06-02201310.1109/NEWCAS.2013.6573590https://infoscience.epfl.ch/handle/20.500.14299/92531WOS:000327392600029We present a doubly parallelized layered quasi-cyclic low density parity-check decoder for the emerging IEEE 802.11ad multigigabit wireless standard. The decoding algorithm is equivalent to a nonparallelized layered decoder and, thus, retains its favorable convergence characteristics, which are known to be superior to those of flooding schedule based decoders. The proposed architecture was synthesized using a TSMC 40 nm CMOS technology, resulting in a cell area of 0.18 mm2 and a clock frequency of 850 MHz. At this clock frequency, the decoder achieves a coded throughput of 3.12 Gbps, thus meeting the throughput requirements when using both the mandatory BPSK modulation and the optional QPSK modulation.text::conference output::conference proceedings::conference paper