Rahimian Omam, SomayyehPavlidis, VasileiosDe Micheli, Giovanni2011-12-142011-12-142011-12-14201110.1007/978-3-642-24154-3_27https://infoscience.epfl.ch/handle/20.500.14299/73168WOS:000306294300027Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce the power consumption while delivering a full swing clock signal to the sink nodes. A design method for 3-D resonant clock networks is presented. The proposed design technique supports resonant operation for pre-bond test, an important requirement for 3-D ICs. Several 3-D clock network topologies are explored in a 0.18 μm CMOS technology. Simulation results indicate 43% reduction in the power consumed by the resonant 3-D clock network as compared to a conventional buffered clock network.3-D integrationclock distribution networksresonant clockingtext::conference output::conference proceedings::conference paper