Parandeh-Afshar, HadiVerma, Ajay KumarBrisk, PhilipIenne, Paolo2011-12-162011-12-162011-12-16201010.1109/TVLSI.2009.2014380https://infoscience.epfl.ch/handle/20.500.14299/75650WOS:000276036800006The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP applications, and further opportunities to exploit it can be exposed through systematic data flow transformations that can be applied by a hardware compiler. Field-programmable gate arrays (FPGAs), however, are not particularly well suited to carry-save arithmetic. To address this concern, we introduce the "field programmable counter array" (FPCA), an accelerator for carry-save arithmetic intended for integration into an FPGA as an alternative to DSP blocks. In addition to multiplication and multiply accumulation, the FPCA can accelerate more general carry-save operations, such as multi-input addition (e. g., add k > 2 integers) and multipliers that have been fused with other adders. Our experiments show that the FPCA accelerates a wider variety of applications than DSP blocks and improves performance, area utilization, and energy consumption compared with soft FPGA logic.Carry-save arithmeticfield-programmable gate array (FPGA)generalized parallel counter (GPC)Generalized Parallel Counterstext::journal::journal article::research article