A 58mW 1.2 mm 2 HSDPA Turbo Decoder ASIC in 0.13 μm CMOS

Benkeser, ChristianBurg, AndreasCupaiuolo, TeoHuang, Qiuting2011-06-062011-06-062011-06-06200810.1109/ISSCC.2008.4523158https://infoscience.epfl.ch/handle/20.500.14299/68389WOS:000262328200010This paper presents the implementation of the 1.2 mm2 HSDPA turbo decoder ASIC in 0.13 mum CMOS achieves a measured maximum frequency of 246 MHz, which translates to a maximum throughput of 20.2 Mb/s at 5.5 iterations. The peak throughput of 10.8 Mb/s required for HSDPA is achieved at 58 mW and an energy efficiency of 0.7 nJ/b/iter. The number of iterations versus input SNR, as determined by the implemented stopping criterion, and corresponding power measurements.Channel decodingearly terminationHsdpalow powerturbo codes3G mobile communicationA 58mW 1.2 mm 2 HSDPA Turbo Decoder ASIC in 0.13 μm CMOStext::conference output::conference proceedings::conference paper