Kopta, VladimirPengg, FranzLe Roux, ErwanEnz, Christian2017-03-052017-03-052017-03-05201310.1109/NEWCAS.2013.6573587https://infoscience.epfl.ch/handle/20.500.14299/134972A 2.4-GHz low power polar transmitter architecture is proposed in this paper. A dynamic biasing circuit, controlled by a digital envelope signal, is used to linearize the input-output characteristic of the overdriven class-C power amplifier. A model of the transmitter is presented and used for initial assessment of the achievable performance in terms of efficiency and linearity. The transmitter is designed in a 65 nm CMOS technology. The transistor-level simulations indicate that the transmitter successfully meets the requirements of the IEEE 802.15.6 standard for wireless body area networks. The simulated amplifier consumes 5 rnA from a 1.2 V supply while delivering 1.8 dBm of output power with a peak efficiency of 26.5 %.TransmittersTransistorsIntegrated circuit modelingMathematical modelPower generationCMOS integrated circuitsDynamic biasingWBANPolar amplifierLow powertext::conference output::conference proceedings::conference paper