A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS

Roth, C.Meinerzhagen, Pascal AndreasStuder, C.Burg, Andreas Peter2011-08-212011-08-212011-08-21201010.1109/ASSCC.2010.5716618https://infoscience.epfl.ch/handle/20.500.14299/70182We present a low-power quasi-cyclic (QC) low density parity check (LDPC) decoder that meets the throughput requirements of the highest-rate (600 Mbps) modes of the IEEE 802.11n WLAN standard. The design is based on the layered offset-min-sum algorithm and is runtime-programmable to process different code matrices (including all rates and block lengths specified by IEEE 802.11n). The register-transfer-level implementation has been optimized for best energy efficiency. The corresponding 90nm CMOS ASIC has a core area of 1.77mm2 and achieves a maximum throughput of 680 Mbps at 346MHz clock frequency and 10 decoding iterations. The measured energy efficiency is 15.8 pJ/bit/iteration at a nominal operating voltage of 1.0V.A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOStext::conference output::conference proceedings::conference paper