Process/Design Co-optimization of Regular Logic Tiles for Double-Gate Silicon Nanowire Transistors

Bobba, ShashikanthGaillardon, Pierre-Emmanuel Julien MarcZhang, JianDe Marchi, MicheleSacchetto, DavideLeblebici, YusufDe Micheli, Giovanni2012-07-102012-07-102012-07-10201210.1145/2765491.2765503https://infoscience.epfl.ch/handle/20.500.14299/83725Ambipolar transistors with on-line configurability to n-type and p-type polarity are desirable for future integrated circuits. Regular logic tiles have been recognized as an efficient layout fabric for ambipolar devices. In this work, we present a process/design co-optimization approach for designing logic tiles for double-gate silicon nanowire field effect transistors (DG- SiNWFET) technology. A compact Verilog-A model of the device is extracted from TCAD simulations. Cell libraries with different tile configurations are mapped to study the performance of DG-SiNWFET technology at various technology nodes. With an optimal tile size comprising of 6 vertically-stacked nanowires, we observe 1.6x improvement in area, 2x decrease in the leakage power and 1.8x improvement in delay when compared to Si- CMOS.Process/Design Co-optimization of Regular Logic Tiles for Double-Gate Silicon Nanowire Transistorstext::conference output::conference proceedings::conference paper