Fazan, Pierre ChristopheOkhonin, Serguei2017-06-132017-06-132017-06-132007https://infoscience.epfl.ch/handle/20.500.14299/138370A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit 16, writing circuits 18 and a refreshing circuit 22 apply input signals to the data storage cells to reverse the variation of the physical parameter with time of at least those cells representing one of the binary logic states by causing a different variation in the physical parameter of cells in one of said states than in the other. <IMAGE>patentCN100466098US7342842DE60218283US2007109896DE60218283AT354852EP1355316US7170807US6982918CN1647212US2005128851US2004240306AU2003215662WO03088255EP1355316EP135531728676391