Fab-to-fab and run-to-run variability in 130 nm and 65 nm CMOS technologies exposed to ultra-high TID

Termo, G.Borghello, G.Faccio, F.Michelis, S.Koukab, A.Sallese, J. -M.2023-04-102023-04-102023-04-102023-01-0110.1088/1748-0221/18/01/C01061https://infoscience.epfl.ch/handle/20.500.14299/196760WOS:000940721800006The discovery of a large fab-to-fab variability in the TID response of the CMOS technologies used in the design of ASICs for the particle detectors of the HL-LHC triggered a monitoring effort to verify the consistency of the CMOS production process over time. As of 2014, 22 chips from 3 different fabs in 130 nm CMOS technology and 11 chips from 2 different fabs in 65 nm CMOS technology have been irradiated to ultra-high doses, ranging from 100 Mrad(SiO2) to 1 Grad(SiO2). This unprecedented monitoring effort revealed significant fab-to-fab and run-to-run variability, both dependent on the characteristics of the MOS transistors.Instruments & Instrumentationradiation damage to electronic componentsradiation-hard electronicsinspection with x-raysmodels and simulationsdose-rate sensitivitytransistor variabilityimpactgateperformanceFab-to-fab and run-to-run variability in 130 nm and 65 nm CMOS technologies exposed to ultra-high TIDtext::journal::journal article::research article