Yilmaz, GurkanDehollain, Catherine2017-02-172017-02-172017-02-17201610.1109/NORCHIP.2016.7792883https://infoscience.epfl.ch/handle/20.500.14299/134383WOS:000391620400010This paper presents a frequency synthesizer based on a phase locked loop (PLL) targeting low jitter applications. The frequency generator covers a range wider than a decade, more explicitly from 20 to 300 MHz. Thanks to a 4-stage ring oscillator, it can provide quadrature signals and exhibit a -117 dBc/Hz phase noise at an offset of 1 MHz from the carrier. Settling time simulations on MATLAB and Cadence Spectre match with measurement results, which yield maximum 1.3 mu s (or 26 reference cycles) for N to N+1 switching, while N denotes the integer division ratio. PLL core draws a current less than 5 mA when it is supplied from a 1.8 V dc supply. PLL is driven by a 20 MHz clock source having 0.67 ps rms jitter. At 200 MHz, the circuit provides a differential output with 2.05 ps rms jitter (equivalent to 0.41 mUI) within an integration window from 10 Hz to 40 MHz and creates a reference spur lower than -70 dBc.phase-locked loopclock generationreference spurphase noisejittertext::conference output::conference proceedings::conference paper