Seiculescu, CiprianMurali, SrinivasanBenini, LucaDe Micheli, Giovanni2010-07-202010-07-202010-07-20201010.1109/TCAD.2010.2061610https://infoscience.epfl.ch/handle/20.500.14299/51740WOS:000284417400012Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs). Designing an efficient network on chip (NoC) interconnect for a 3-D SoC that meets not only the application performance constraints but also the constraints imposed by the 3-D technology is a significant challenge. In this paper, we present a design tool, SunFloor 3D, to synthesize application-specific 3-D NoCs. The proposed tool determines the best NoC topology for the application, finds paths for the communication flows, assigns the network components to the 3-D layers, and places them in each layer. We perform experiments on several SoC benchmarks and present a comparative study between 3-D and 2-D NoC designs. Our studies show large improvements in interconnect power consumption (average of 38%) and delay (average of 13%) for the 3-D NoC when compared to the corresponding 2-D implementation. Our studies also show that the synthesized topologies result in large power (average of 54%) and delay savings (average of 21%) when compared to standard topologies.3-D integrated circuits (3D-ICs)networks on chip (NoC)placementsynthesistopologyOn-ChipInterconnection NetworksDesignGenerationArchitecturesPerformancetext::journal::journal article::research article