Arian, A.Saberi, M.Hosseini-Khayat, S.Lotfi, R.Leblebici, Y.2012-06-142012-06-142012-06-14201210.1007/s10470-011-9812-5https://infoscience.epfl.ch/handle/20.500.14299/81863WOS:000304101200024A new architecture for successive-approximation register analog-to-digital converters (SAR ADC) using generalized non-binary search algorithm is proposed to reduce the complexity and power consumption of the digital circuitry. The proposed architecture is based on the split capacitive-array DAC with a simple switching logic as compared to the conventional non-binary SAR ADC architecture. A 10-bit 50-MS/s SAR ADC is designed based on the proposed architecture in a 0.18 1 mu m CMOS technology. Simulation results show that at a supply voltage of 1.2 V, the SAR ADC achieves a peak signal-to-noise-and-distortion ratio of 59.5 dB, and a power consumption of 1.3 mW, resulting in a figure of merit of 33 fJ/conversion-step.Digital-to-analog converterRedundant successive approximation ADCRedundant search algorithmSplit capacitive-array DACHigh speed SAR ADCDigital Error-CorrectionCmostext::journal::journal article::research article