Moctar, YehdhihStojilovic, MirjanaBrisk, Philip2019-06-182019-06-182019-06-182018-01-0110.1109/FPL.2018.00011https://infoscience.epfl.ch/handle/20.500.14299/157550WOS:000460538500004This paper describes a deterministic and parallel implementation of the VPR routability-driven router for FPGAs. We considered two parallefization strategies: (1) routing multiple nets in parallel; and (2) routing one net at a time, while parallelizing the Maze Expansion step. Using eight threads running on eight cores, the two methods achieved speedups of 1.84 x and 3.67 x, respectively, compared to VPR's single threaded routability-driven router. Removing the determinism requirement increased these respective speedups to 2.67 x and 5.46 x, while sacrificing the guarantee of reproducible results.Computer Science, Hardware & ArchitectureComputer Science, Software EngineeringComputer Sciencetext::conference output::conference proceedings::conference paper