Pavia, Juan MataScandini, MarioLindner, ScottWolf, MartinCharbon, Edoardo2015-12-022015-12-022015-12-02201510.1109/Jssc.2015.2467170https://infoscience.epfl.ch/handle/20.500.14299/121190WOS:000362359700016A 1 x 400 array of backside-illuminated SPADs fabricated in 130 nm 3D IC CMOS technology is presented. Sensing is performed in the top tier substrate and time-to-digital conversion in the bottom tier. Clusters of eight pixels are connected to a winner-take-all circuit with collision detection capabilities to realise an efficient sharing of the time-to-digital converter (TDC). The sensor's 100 TDCs are based on a dual-frequency architecture enabling 30 pJ per conversion at a rate of 13.3 ms/s per TDC. The resolution (1 LSB) of the TDCs is 49.7 ps with a standard deviation of 0.8 ps across the entire array; the mean DNL is +/- 0.44 LSB and the mean INL is +/- 0.47. The chip was designed for use in near-infrared optical tomography (NIROT) systems for brain imaging and diagnostics. Measurements performed on a silicon phantom proved its suitability for NIROT applications.Near-infrared optical tomography (NIROT)near-infrared spectroscopy (NIRS)optical tomography (OT)single-photon avalanche diode (SPAD)single-photon imagingtime correlated single photon counting (TCSPC)time-of-flight imagingtime-resolved imagingtime-to-digital converter (TDC)text::journal::journal article::research article