Incandela, R. M.Song, L.Homulle, H.A.R.Sebastiano, F.Charbon, E.Vladimirescu, A.2018-08-132018-08-132018-08-132017-10-1610.1109/ESSDERC.2017.8066591https://infoscience.epfl.ch/handle/20.500.14299/147733The characterization of nanometer CMOS transistors of different aspect ratios at deep-cryogenic temperatures (4 K and 100 mK) is presented for two standard CMOS technologies (40 nm and 160 nm). A detailed understanding of the device physics at those temperatures was developed and captured in an augmented MOS11/PSP model. The accuracy of the proposed model is demonstrated by matching simulations and measurements for DC and time-domain at 4 K and, for the first time, at 100 mK.text::conference output::conference proceedings::conference paper