An, HyochanVenkatesan, SiddharthSchiferl, SamWesley, TimZhang, QiruiWang, JingchengChoo, KyojinLiu, ShiyuLiu, BowenLi, ZiyunZhong, HengfeiGong, LuyaoBlaauw, DavidDreslinski, RonaldSylvester, DennisKim, Hun Seok2022-04-012022-04-012022-04-01202010.1109/VLSICircuits18222.2020.9162810https://infoscience.epfl.ch/handle/20.500.14299/186841We propose an ultra-low power (ULP) Image Signal Processor (ISP) that performs on-the-fly in-processing frame (de)compression and hierarchical event recognition to exploit the temporal and spatial sparsity in an image sequence to achieve a 16× imaging system energy gain. The ISP is fabricated in 40 nm CMOS and consumes only 170 μW at 5 fps for neural network-based intruder detection and 192× compressed image recording.text::conference output::conference proceedings::conference paper