Tang, XifanGaillardon, Pierre-EmmanuelDe Micheli, Giovanni2014-09-302014-09-302014-09-30201410.1109/FPT.2014.7082777https://infoscience.epfl.ch/handle/20.500.14299/107146The routing architecture, heavily using programmable switches, dominates the area, delay and power of <i>Field Programmable Gate Arrays</i> (FPGAs). <i>Resistive Random Access Memories</i> (RRAMs) enable high-performance routing architectures through the replacement of <i>Static Random Access Memory</i> (SRAM)-based programming switches. Exploiting the very low <i>on</i>-resistance state achievable by RRAMs, RRAM-based routing multiplexers can be used to significantly reduce the FPGA routing delays. In addition, RRAM-based routing architectures are less sensitive to supply voltage reductions and show promises in low-power FPGA designs. In this paper, we propose a near- V_t low-power RRAM-based FPGA where both delay and power reductions are achieved. Experimental results demonstrate that a near-V_t RRAM-based FPGA design leads to a 15% area shrink, a 10% delay reduction, and a 65% power improvement, compared to a conventional FPGA design for a given technology node. To achieve low _on-resistance values, RRAMs typically require high programming currents. In other word, they need relatively large programming transistors, potentially resulting in area, delay and power inefficiencies. We also present a design methodology to properly size the programming transistors of RRAMs in order to further improve the area-efficiency. Experimental results show that a correct programming transistor sizing strategy contributes to further 18% area and 2% delay shrink, compared to the initial near-V_t RRAM-based FPGA.text::conference output::conference proceedings::conference paper