Constantin, Jeremy Hugues-FelixBonetti, AndreaTeman, Adam ShmuelMüller, Thomas ChristophSchmid, Lorenz FlavioBurg, Andreas Peter2016-06-132016-06-132016-06-13201610.1109/ESSCIRC.2016.7598292https://infoscience.epfl.ch/handle/20.500.14299/126620WOS:000386656300063This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction types currently in flight in the pipeline. To this end, we employ a custom designed clock generation unit, capable of immediate glitch-free adjustments of the clock period over a wide range with fine granularity. Our chip measurements in 28nm FD-SOI technology show that DynOR provides an average speedup of 19% in program execution over a wide range of operating conditions, with a peak speedup for certain applications of up to 41%. Furthermore, this speedup can be traded off against energy, to reduce the chip power consumption for a typical die by up to 15%, compared to a static clocking scheme based on worst case excitation.dynamic clockingtiming marginsmicroprocessor28nm FD-SOIsilicon implementationOpenRISCtext::conference output::conference proceedings::conference paper