Pastre, M.Kayal, M.Schmid, H.Huber, A.Zwahlen, P.Nguyen, A. M.Dong, Y.2010-10-212010-10-212010-10-21200910.1109/ESSCIRC.2009.53260332-s2.0-72849131449https://infoscience.epfl.ch/handle/20.500.14299/55943WOS:000276195800064This paper presents a 5th-order ΔΣ capacitive accelerometer. The ΔΣ loop is implemented in mixed signal, the global 5th-order filter having a 2nd-order analog and a 3rd-order digital part. The system can be used with a wide range of sensors, because the mixed-signal front end is programmable. The ASIC developed comprises a voltage-mode preamplifier, two parallel demodulators implementing CDS, and a 7-bit Flash ADC. The latter drives a 3rd-order digital filter, which can be configured for different sensor parameters in order to ensure overall loop stability and optimize the noise performance. With a low-noise MEMS sensor, the system achieves a 19-bit DR and a 16-bit SNR, both over a 300Hz bandwidth.text::conference output::conference proceedings::conference paper