Green, M. M.Pisani, M. B.Dehollain, C.2010-05-212010-05-212010-05-21200810.1109/ISCAS.2008.45415212-s2.0-51749107473https://infoscience.epfl.ch/handle/20.500.14299/50261The design of distributed amplifiers in a CMOS process is investigated. In particular, the impact of parasitic elements from the transistors and from interstage inductors is studied. A methodology for determining an optimum design, including the number of stages, without needing a complete inductor model at the outset, is presented. This proposed methodology reduces the time and complexity of a distributed amplifier design while at the same time allowing the designer to gain more insight into the circuit's behavior. ©2008 IEEE.CMOS distributed amplifierscircuit behaviordistributed amplifier designtransistorsCMOS analogue integrated circuitscomputational complexitydistributed amplifiersintegrated circuit designtext::conference output::conference proceedings::conference paper