Powell, Michael D.Yang, Se-HyunFalsafi, BabakRoy, KaushikVijaykumar, T. N.2009-04-062009-04-062009-04-06200010.1109/LPE.2000.876763https://infoscience.epfl.ch/handle/20.500.14299/36918Deep-submicron CMOS designs have resulted in large leakage energy dissipation in microprocessors. While SRAM cells in on-chip cache memories always contribute to this leakage, there is a large variability in active cell usage both within and across applications. This paper explores an integrated architectural and circuit-level approach to reducing leakage energy dissipation in instruction caches. We propose, gated-V_dd, a circuit-level technique to gate the supply voltage and reduce leakage in unused SRAM cells. Our results indicate that gated-V_dd together with a novel resizable cache architecture reduces energy-delay by 62% with minimal impact on performancetext::conference output::conference proceedings::conference paper