Najmzadeh, MohammadBoucart, KathyRiess, WalterIonescu, Adrian Mihai2010-08-102010-08-102010-08-10201010.1016/j.sse.2010.04.037https://infoscience.epfl.ch/handle/20.500.14299/52111WOS:000280322300019This paper reports all-silicon asymmetrically strained Tunnel FET architectures that feature improved subthreshold swing and Ion/Ioff characteristics. We demonstrate that a lateral strain profile corresponding to at least 0.2 eV band-gap shrinkage at the BTB source junction could act as an optimized performance Tunnel FET enabling the cancellation of the drain threshold voltage. To implement a real device, we demonstrate using GAA Si NW with asymmetric strain profile using two local stressor technologies to have >4–5 GPa peak of lateral uniaxial tensile stress in the Si NW.Tunnel FETBand-to-band tunnelingLocal lateral uniaxial tensile strainAsymmetric strain profileLocal strain engineeringLocal band-gap modulationSubthreshold swingCMOS downscalingMulti-gateSi nanowireFP7text::journal::journal article::research article