Subthreshold Logic for Low-Area and Energy Efficient True Random Number Generator

Coustans, MathieuCherkaoui, AbdelkarimFesquet, LaurentTerrier, ChristianSalgado, StephanieEberhardt, ThomasKayal, Maher2019-01-232019-01-232019-01-232018-01-0110.1109/CoolChips.2018.8373081https://infoscience.epfl.ch/handle/20.500.14299/153813WOS:000455046600009This paper discusses the advantages of subthreshold logic for True Random Number Generators (TRNG). In this work, the entropy is modeled, and a lower bound of Shannon's entropy per output bit can quickly be estimated. Thanks to this model, sizing TRNGs in subthreshold logic is quite simple and defining design guidelines for low-energy and low-area TRNGs is straightforward. A TRNG in 180nm CMOS technology has been designed, demonstrating low complexity (305 gates) and energy efficacy (30pJ/bit) at 0.5 Kbit/s.Computer Science, Hardware & ArchitectureEngineering, Electrical & ElectronicComputer ScienceEngineeringapplied cryptographyrandom numbers generatorsasynchronous circuitssubthreshold logicSubthreshold Logic for Low-Area and Energy Efficient True Random Number Generatortext::conference output::conference proceedings::conference paper