Parandeh-Afshar, HadiNeogy, ArkosnatoBrisk, PhilipIenne, Paolo2012-06-252012-06-252012-06-25201110.1145/2068716.2068725https://infoscience.epfl.ch/handle/20.500.14299/82246WOS:000299337900009Compressor trees are a class of circuits that generalizes multioperand addition and the partial product reduction trees of parallel multipliers using carry-save arithmetic. Compressor trees naturally occur in many DSP applications, such as FIR filters, and, in the more general case, their use can be maximized through the application of high-level transformations to arithmetically intensive data flow graphs. Due to the presence of carry-chains, it has long been thought that trees of 2- or 3-input carry-propagate adders are more efficient than compressor trees for FPGA synthesis; however, this is not the case. This article presents a heuristic for FPGA synthesis of compressor trees that outperforms adder trees and exploits carry-chains when possible. The experimental results show that, on average, the use of compressor trees can reduce critical path delay by 33% and 45% respectively, compared to adder trees synthesized on the Xilinx Virtex-5 and Altera Stratix III FPGAs.AlgorithmsPerformanceField Programamble Gate Array (FPGA)look-up table (LUT)carry chaincompressor treeMultiplierDesignCircuitstext::journal::journal article::research article