Gong, JiangCharbon, EdoardoSebastiano, FabioBabaie, Masoud2022-01-012022-01-012022-01-01202210.1109/JSSC.2021.3105335https://infoscience.epfl.ch/handle/20.500.14299/184189WOS:000732880200001This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing any power-hungry isolation buffers, the proposed phase detector dramatically suppresses the reference spurs by both minimizing the modulated capacitance seen by the voltage-controlled oscillator (VCO) tank and by reducing the duty cycle of the sampling clock. A 50-mu W RF-dividerless frequency-tracking loop is also introduced to lock the CSPLL robustly when the VCO faces a sudden frequency disturbance. Fabricated in a 40-nm CMOS process, the prototype CSPLL occupies a core area of 0.13 mm(2) and synthesizes 9.6-to-12-GHz tones using a 100-MHz reference. At 11.2 GHz, it achieves a reference spur of -77.3 dBc and an RMS jitter of 48.6 fs while consuming 5 mW.Engineering, Electrical & ElectronicEngineeringvoltage-controlled oscillatorspartial dischargesphase locked loopsradio frequencyclocksjitterdetectorscharge-sampling phase detector (cspd)charge-sampling phase-locked loop (cspll)divider-less frequency-tracking loop (ftl)in-band phase noise (pn)low jitterreference spursub-samplingcommon-mode resonancenoisepowercmososcillatortext::journal::journal article::research article