Worm, FrédéricThiran, PatrickDe Micheli, GiovanniIenne, Paolo2005-08-082005-08-082005-08-08200510.1109/ISCAS.2005.1465099https://infoscience.epfl.ch/handle/20.500.14299/215203Networks-on-chip provide an elegant framework to efficiently reuse predesigned cores. However, reuse of cores is jeopardized by new deep sub-micron noise effects that challenge the reliability of CMOS technology. Moreover, noise margins are further reduced as supply voltages scale down. We advocate that self-calibrating techniques will be needed to maintain an acceptable design trade-off between energy, performance, and reliability. As a result, self-calibrating techniques have to be integrated within networks-on-chip. This paper presents a self-calibrating link and discusses qualitatively the problem of controlling adaptively its voltage and frequency.Robust Designtext::conference output::conference proceedings::conference paper