Constantin, Jeremy Hugues-FelixDogan, AhmedAndersson, OskarMeinerzhagen, Pascal AndreasRodrigues, JoachimAtienza Alonso, DavidBurg, Andreas Peter2013-10-242013-10-242013-10-24201310.1007/978-3-642-45073-0_5https://infoscience.epfl.ch/handle/20.500.14299/96416Compressed sensing (CS) is a universal low-complexity data compression technique for signals that have a sparse representation in some domain. While CS data compression can be done both in the analog- and digital domain, digital implementations are often used on low-power sensor nodes, where an ultra-low-power (ULP) processor carries out the algorithm on Nyquist-rate sampled data. In such systems an energy-efficient implementation of the CS compression kernel is a vital ingredient to maximize battery lifetime. In this paper, we propose an application-specific instruction-set processor (ASIP) processor that has been optimized for CS data compression and for operation in the subthreshold (sub-VT) regime. The design is equipped with specific sub-VT capable standard-cell based memories, to enable low-voltage operation with low leakage. Our results show that the proposed ASIP accomplishes 62× speed-up and 11.6× power savings with respect to a straightforward CS implementation running on the baseline low-power processor without instruction set extensions.Ultra-Low-Power ProcessorApplication-Specific Instruction Set ProcessorInstruction Set ExtensionsSub-VT OperationSub- VT Embedded MemoriesCompressed Sensingtext::book/monograph::book part or chapter