Kluter, TheoBurri, SamuelBrisk, PhilipCharbon, EdoardoIenne, Paolo2014-10-232014-10-232014-10-23201410.1145/2576877https://infoscience.epfl.ch/handle/20.500.14299/107948WOS:000341066600001Instruction set extensions (ISEs) improve the performance and energy consumption of application-specific processors. ISEs can use architecturally visible storage (AVS), localized compiler-controlled memories, to provide higher I/O bandwidth than reading data from the processor pipeline. AVS creates coherence and consistence problems with the data cache. Although a hardware coherence protocol could solve the problem, this approach is costly for a single-processor system. As a low-cost alternative, we introduce Virtual Ways, which ensures coherence through a reduced form of inclusion between the data cache and AVS. Virtual Ways achieve higher performance and lower energy consumption than using a hardware coherence protocol.PerformanceDesignExperimentationInstruction set extensionarchitecturally visible storagememory coherencememory consistenceVirtual Waystext::journal::journal article::research article