Design and Realization of a Fault-Tolerant 90nm Cryptographic Engine Capable of Performing under Massive Defect Density

Stanisavljevic, MilosGürkaynak, Frank KaganSchmid, AlexandreLeblebici, YusufGabrani, Maria2007-06-262007-06-262007-06-26200710.1145/1228784.1228837https://infoscience.epfl.ch/handle/20.500.14299/9352WOS:000268001100041This paper presents a new approach for assessing the reliability of nanometer-scale devices prior to fabrication and a practical reliability architecture realization. A four-layer architecture exhibiting a large immunity to permanent as well as random failures is used. Characteristics of the averaging/thresholding layer are emphasized. A complete tool based on Monte Carlo simulation for a-priori functional fault tolerance analysis was used for analysis of distinctive cases and topologies. A full chip CMOS integrated design of the 128-bit AES cryptography algorithm with multiple cores that incorporate reliability architectures is shown.fault-tolerant architecturehigh defect densityreliability of submicron and nanoelectronic systemsAES cryptography algorithmDesign and Realization of a Fault-Tolerant 90nm Cryptographic Engine Capable of Performing under Massive Defect Densitytext::conference output::conference proceedings::conference paper