Dlugosz, RafalTalaska, TomaszSzulc, MichalSniatala, PawelStadelmann, PatrickTanner, SteveFarine, Pierre-André2013-02-252013-02-252013-02-25201210.1109/MIEL.2012.6222889https://infoscience.epfl.ch/handle/20.500.14299/89118WOS:000309119600087The paper presents a low power and low chip area decimation filter for a 15-bits Σ-Δ analog-to-digital converter (ADC) designed for a flywheel MEMS gyroscope. In contrary to typical solutions, in which decimation is performed after each filtering stage, in the proposed approach all filter sections operate at the sampling frequency of the modulator. The low power dissipation is in this case achieved by substantially simpler structure of particular stages. By selecting the oversampling ratio (OSR) of the modulator sufficiently large, e.g. 200, the decimation filter composed of Finite Impulse Response (FIR) filters with equal coefficients does not distort the passband signal. The low chip area results from eliminating a complex selective filter usually placed at the end of the filtering chain in the decimation filter.Delay linesFinite impulse response filterFrequency modulationNoiseSignal resolutionTransistorstext::conference output::conference proceedings::conference paper