Wang, ShenjieDehollain, CatherineHong, Zhiliang2012-06-292012-06-292012-06-29201210.1007/s10470-012-9832-9https://infoscience.epfl.ch/handle/20.500.14299/82486WOS:000304874300027Averaging network is adopted to reduce the front-end amplifier's offset in the flash analog-to-digital converter (ADC) commonly at the cost of the boundary threshold error. Such error worsens the integral-nonlinearity and introduces distortion. An averaging termination scheme using intended asymmetric spatial filter response is proposed to overcome this problem. It matches the impulse response window width, W-IR, to the active zero-crossing response window width, W-ZX at the boundary of network. Analysis and simulation show that by tuning the ratio between termination resistor R-T and averaging resistor R-1, the boundary error is reduced as close as to 1%. This method provides sufficient reliability since the resistance matching can be fabricated as high as 1% in modern CMOS technology. Its feasibility for the flash ADC has been validated by a 1GS/s 4-bit flash converter.enAsymmetric spatial filterAveraging networkOffsetFlash ADCResistorCmos Adctext::journal::journal article::research article