Ye, Terry TaoDe Micheli, GiovanniBenini, Luca2011-05-052011-05-052011-05-05200210.1145/513918.514051https://infoscience.epfl.ch/handle/20.500.14299/67042In this paper, we introduce a framework to estimate the power consumption on switch fabrics in network routers. We propose different modeling methodologies for node switches, internal buffers and interconnect wires inside switch fabric architectures. A simulation platform is also implemented to trace the dynamic power consumption with bit-level accuracy. Using this framework, four switch fabric architectures are analyzed under different traffic throughput and different numbers of ingress/egress ports. This framework and analysis can be applied to the architectural exploration for low power high performance network router designs.text::conference output::conference proceedings::conference paper