Brunet, S. CasaleBezati, E.Alberti, C.Mattavelli, M.Amaldi, E.Janneck, J. W.2014-06-022014-06-022014-06-02201310.1109/SiPS.2013.6674501https://infoscience.epfl.ch/handle/20.500.14299/103874WOS:000332832800031In this paper we propose a design methodology to partition dataflow applications on a multi clock domain architecture. This work shows how starting from a high level dataflow representation of a dynamic program it is possible to reduce the overall power consumption without impacting the performances. Two different approaches are illustrated, both based on the post-processing and analysis of the causation trace of a dataflow program. Methodology and experimental results are demonstrated in an at-size scenario using an MPEG-4 Simple Profile decoder.MCDGALSdataflowco-explorationtext::conference output::conference proceedings::conference paper