Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesis

Cacciotti, MattiaCamus, VincentSchlachter, JeremyPezzotta, AlessandroEnz, Christian2018-09-062018-09-062018-09-062018-09-0610.1109/SOCC.2018.8618490https://infoscience.epfl.ch/handle/20.500.14299/148150In this paper, the hardware acceleration of a tone-mapping algorithm for High-Dynamic-Range image processing is presented. Starting from the C++ source code, High-Level Synthesis has been performed using Xilinx SDSoC for a Xilinx Zynq SoC device. After an initial code optimization to improve the memory access bottleneck, SDSoC pragmas have been introduced to boost system performance through an increased parallelism. Preliminary results have shown significant reductions in the execution time and the energy consumption compared to the conventional software implementation.Heterogeneous systemsFPGAHigh-level synthesisHardware-software co-designImage tone mappingHardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesistext::conference output::conference proceedings::conference paper