Leblebici, YusufToifl, ThomasKull, Lukas2014-01-202014-01-20201410.5075/epfl-thesis-6037https://infoscience.epfl.ch/handle/20.500.14299/99586urn:nbn:ch:bel-epfl-thesis6037-8enADCanalog-to-digital converterSARsuccessive approximationasynchronousredundantalternate comparatorsconstant commonmodeoffset compensationpass-gate selection clockingR-3Rinterleaved ADCpassive samplerHigh-Speed CMOS ADC Design for 100Gb/s Communication Systemsthesis::doctoral thesis