Simon, William AndrewGalicia, Juan-MartinLevisse, Alexandre Sébastien JulienZapater Sancho, MarinaAtienza Alonso, David2019-04-032019-04-032019-04-032019-06-0210.1145/3316781.3317741https://infoscience.epfl.ch/handle/20.500.14299/155877WOS:000482058200083In-Memory Computing (IMC) solutions, and particularly bitline computing in SRAM, appear promising as they mitigate one of the most energy consuming aspects in computation: data movement. In this work we propose a fast (2.4Ghz for bitwise operations and 2.4/1.5Ghz for 32/64bit additions respectively), reliable (no read disturb issues) and wide voltage range (from 0.6 to 1V) 6T SRAM-based IMC architecture using local bitlines and a fast carry adder pitched below the memory subarray. We verify the proposed architecture through layout and variability aware simulations in 28nm bulk high performances technology PDK.In-Memory ProcessingIMPIn-Memory ComputingIMCbitline Computingfast carry rippleadderlocal bitlitneread disturbtext::conference output::conference proceedings::conference paper