Giterman, RobertBonetti, AndreaBravo, Ester VicarioNoy, TzachiTeman, AdamBurg, Andreas2020-04-182020-04-182020-04-182020-04-0110.1109/TCSI.2020.2971695https://infoscience.epfl.ch/handle/20.500.14299/168252WOS:000522984300013The rise of data-intensive applications has resulted in an increasing demand for high-density and low-power on-chip embedded memories. Gain-cell embedded DRAM (GC-eDRAM) is a logic-compatible alternative to conventional static random access memory (SRAM) which offers higher density, lower leakage power, and two-ported operation. However, in order to maintain the stored data, GC-eDRAM requires periodic refresh cycles, which are determined according to the worst-case data retention time (DRT) across process, voltage and temperature (PVT) variations. Even though several DRT characterization methodologies have been reported in literature, they often require unfeasible run-times for accurate DRT evaluation, or they result in highly pessimistic design margins due to their inaccuracy. In this work, we propose an current-based DRT (IDRT) characterization methodology that enables accurate DRT evaluation across process variations without the need for a large number of costly electronic design automation (EDA) software licenses. The presented approach is compared with other DRT characterization methodologies for both accuracy and run-time across several gain-cell structures at different process technologies, providing less than a 4% DRT error and over 100x shorter run-time compared to a conventional DRT evaluation methodology.Engineering, Electrical & ElectronicEngineeringembedded dynamic random access memory (edram)gain-cells (gcs)retention timeembedded memorytext::journal::journal article::research article