Akkaya, AycaCelik, FiratLeblebici, Yusuf2021-07-032021-07-032021-07-032021-07-0110.1109/TCSI.2021.3074039https://infoscience.epfl.ch/handle/20.500.14299/179613WOS:000658349200002This paper presents a low-power single-channel 8-bit loop-unrolled (LU) successive approximation register (SAR) analog-to-digital-converter (ADC) with a novel common-mode adaptive background comparator offset calibration scheme. LU-SAR ADCs use multiple comparators to reduce the SAR loop delay. Offset mismatch between the comparators severely degrades the effective resolution. This paper addresses the common-mode voltage variation in the LU-SAR architecture due to comparator kickback and the problems related to the common-mode dependency of the comparator offset. The proposed offset calibration scheme ensures that the comparators are calibrated at the same input common-mode voltage at which they each operate during the SAR conversion to prevent the common-mode dependent offset mismatch between them. Moreover, the proposed ADC design exploits the common-mode variation immunity of the proposed calibration scheme to optimize the figure-of-merit (FoM). The prototype ADC manufactured in 28nm FDSOI CMOS achieves 42.57dB signal-to-noise-and-distortion ratio and 22.8fJ/conv.-step FoM at 800MS/s with near Nyquist frequency input, and occupies an area of 0.0037mm(2).Engineering, Electrical & ElectronicEngineeringcalibrationclocksdelaysregistersredundancysilicon-on-insulatorprototypesanalog-to-digital converter (adc)successive approximation register (sar)loop-unrolled (lu)multicomparatoroffset calibrationsingle-channelcomparators1.25-gs/sspeed6-bitsndrtext::journal::journal article::research article