Cevrero, AlessandroBeanato, GiuliaAthanasopoulos, PanagiotisLeblebici, Yusuf2012-06-142012-06-142012-06-142012https://infoscience.epfl.ch/handle/20.500.14299/81874A novel modular, cost e ffective 3D multi-processor architecture is presented. Auto-configurable and independently testable identical dies are stacked exploiting Through-Silicon-Vias (TSV) technology, allowing to target different market segments by selecting the appropriate number of layers. For the purpose of evaluation, dies have been fabricated using a commodity UMC 90nm CMOS process and stacked using a in-house, Via-Last copper TSV process. Each die, featuring four cores interconnected by a Network-on-Chip (NoC), has been designed for a maximum operating frequency of 400MHz resulting in 3.2Gbps data bandwidth.Towards Cost Effective Multi-Core Processor Platforms Using 3-D Stacking Technologytext::conference output::conference proceedings::conference paper