Tajalli, ArminMuller, PaulAtarodi, MojtabaLeblebici, Yusuf2007-06-212007-06-212007-06-21200610.1109/ISCAS.2006.1693033https://infoscience.epfl.ch/handle/20.500.14299/9174This paper presents an approach for analyzing and modeling of gated-oscillator (GO) -based CDRs and predicting their performance aspects such as jitter tolerance (JTOL) and frequency tolerance (FTOL). It is shown that high JTOL of this topology in addition to its acceptable FTOL and flexible topology, have made it very suitable for short-haul multi-rate applications.CMOS Integrated circuitsClock and data recoveryJitter tolerancetext::conference output::conference proceedings::conference paper