Anders, J.Reymond, S.Boero, G.Scheffler, K.2010-11-302010-11-302010-11-30200910.1007/978-3-540-92841-6_22https://infoscience.epfl.ch/handle/20.500.14299/60010WOS:000268245600022In this paper a novel architecture for an integrated NMR receiver front-end for surgical guidance applications is described. While the chip consumes only 9 mA supply current from a 3.3 V power supply it has a measured input referred noise density of 0.7 nV/root Hz. The receiver consists of the reception coil, an on-chip tuning capacitor an LNA and a 50 Omega output buffer. The system is designedfor operation in a B-0-field of 1.5 T corresponding to a frequency of 63MHz. It is implemented in a 0.35 mu m CMOS high voltage process and occupies a chip area of 500 mu m x 760 mu m.CmosNmrMriSurgical Guidancetext::conference output::conference proceedings::conference paper