Bit vs. Symbol Interleaving for Parallel Concatenated Trellis Coded Modulation
This paper compares bit versus symbol interleaving for parallel-concatenated trellis-coded turbo codes, employing the turbo encoder structure proposed in Benedetto et al., (1996). To compare systems optimized with the same techniques, the paper extends the turbo-encoder design procedure proposed in Fragouli et al. (2001), to bit-interleaved systems. We discuss a method to jointly design the multiple required interleavers for the bit-interleaved system, and a procedure to select constituent encoders that can take advantage of the interleaver structure to achieve a low error floor. Simulation results for the designed bit-interleaved system show better performance than bit-interleaved performance reported in the literature. The symbol-interleaved system though achieves an earlier convergence, especially with an increased number of decoder iterations, but at the cost of a slightly higher error floor.
Record created on 2007-02-02, modified on 2016-08-08