000099564 001__ 99564
000099564 005__ 20190330091446.0
000099564 0247_ $$2doi$$a10.1155/2007/37627
000099564 037__ $$aARTICLE
000099564 245__ $$aA Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Guarantees
000099564 260__ $$bHindawi Publications$$c2007
000099564 269__ $$a2007
000099564 336__ $$aJournal Articles
000099564 520__ $$aNetworks on Chips (NoCs) are required to tackle the increasing delay and poor scalability issues of bus-based communication architectures. Many of today’s NoC designs are based on single path routing. By utilizing multiple paths for routing, congestion in the network is reduced significantly, which translates to improved network performance or reduced network bandwidth requirements and power consumption. Multiple paths can also be utilized to achieve spatial redundancy, which helps in achieving tolerance against faults or errors in the NoC. A major problem with multipath routing is that packets can reach the destination in an out-of-order fashion, while many applications require in-order packet delivery. In this work, we present a multipath routing strategy that guarantees in-order packet delivery for NoCs. It is based on the idea of routing packets on partially nonintersecting paths and rebuilding packet order at path reconvergent nodes. We present a design methodology that uses the routing strategy to optimally spread the traffic in the NoC to minimize the network bandwidth needs and power consumption. We also integrate support for tolerance against transient and permanent failures in the NoC links in the methodology by utilizing spatial and temporal redundancy for transporting packets. Our experimental studies show large reduction in network bandwidth requirements (36.86% on average) and power consumption (30.51% on average) compared to single-path systems. The area overhead of the proposed scheme is small (a modest 5% increase in network area). Hence, it is practical to be used in the on-chip domain.
000099564 700__ $$0242414$$g171633$$aMurali, Srinivasan
000099564 700__ $$0240268$$g169199$$aAtienza, David
000099564 700__ $$g171049$$aBenini, Luca$$0243773
000099564 700__ $$aDe Micheli, Giovanni$$g167918$$0240269
000099564 773__ $$tVLSI-Design Journal$$q37627
000099564 8564_ $$uhttps://infoscience.epfl.ch/record/99564/files/S1065514X07376274.pdf$$zn/a$$s798420$$yn/a
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000099564 937__ $$aEPFL-ARTICLE-99564
000099564 973__ $$rREVIEWED$$sPUBLISHED$$aEPFL
000099564 980__ $$aARTICLE