Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power

Energy efficiency in microarchitectures has become a necessity. Significant dynamic energy savings can be realized for adaptive storage structures such as caches, issue queues, and register files by disabling unnecessary storage resources. Prior studies have analyzed individual structures and their control. A common theme to these studies is exploration of the configuration space and use of system IPC as feedback to guide reconfiguration. However, when multiple structures adapt in concert, the number of possible configurations increases dramatically, and assigning causal effects to IPC change becomes problematic. To overcome this issue, we introduce designs that are reconfigured solely on local behavior. We introduce a novel cache design that permits direct calculation of efficient configurations. For buffer and queue structures, limited histogramming permits precise resizing control. When applying these techniques we show energy savings of up to 70% on the individual structures, and savings averaging 30% overall for the portion of energy attributed to these structures with an average of 2.1% performance degradation.


Published in:
11th International Conference on Parallel Architectures and Compilation Techniques (PACT), 141-152
Presented at:
11th International Conference on Parallel Architectures and Compilation Techniques (PACT), Charlottesville, Virginia, September 2002
Year:
2002
Keywords:
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 Record created 2006-11-30, last modified 2018-03-17

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