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The transceivers of a wireless sensor network (WSN) have to fulfill the low-power and low-voltage constraints. The WiseNET project has already proven that it is possible to design a receiver working at 1V and consuming less than 2mW. However this transceiver is using OOK and wideband FSK modulations, which have a very poor spectral efficiency. A more complex modulation scheme is therefore needed, which requires an ADC in order to demodulate the signal in the digital domain. The ADC is then becoming the main bottleneck if the low-power consumption is targeted. This thesis aims at studying a next generation WiseNET transceiver using a more spectral efficient phase modulation scheme, particularly the new IEEE 802.15.4 standard, and it focuses on the design of a low-power and low-voltage ADC. The choice of the best receiver architecture depends on many factors, among which the power consumption, the integration suitability, the image rejection, the flicker and quantization noise, etc. Several architectures are analyzed in order to identify the trade-offs and select the most suitable for the IEEE 802.15.4 standard, i.e. a low-IF receiver with a quadrature band-pass ΔΣ modulator. From these considerations, a 2nd-order continuous-time quadrature band-pass ΔΣ modulator was implemented in a 0.18μm standard digital process. The design is focused on the constraints of low power consumption, low supply voltage and low complexity imposed by WSN. The availability of I and Q signals in the low-IF receiver enables a quadrature architecture, which allows to combine signal filtering, image rejection and quantization noise reduction. A continuous-time Gm-C implementation further combines the anti-alias function within the ADC and allows to achieve the 1V operation. The quadrature ΔΣ modulator is clocked at 72MHz and the center frequency is set to 3.75MHz with a bandwidth of 3MHz. The maximum measured signal-to-noise ratio is 36dB and the power consumption is only 450μW under 1V.