A buffer-sizing Algorithm for Networks on Chip using TDMA and credit-based end-to-end Flow Control

When designing a System-on-Chip (SoC) using a Network-on- Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power consumption is due to the buffers in the Network Interfaces (NIs) needed to decouple computation from communication. Having such a decoupling prevents stalling of IP blocks due to the communication interconnect. The size of these buffers is especially important in real-time systems, as there they should be big enough to obtain predictable performance. To ensure that buffers do not overflow, end-to-end flow-control is needed. One form of end-to-end flow-control used in NoCs is credit-based flow-control. This form of flow-control places additional requirements on the buffer sizes, because the flow-control delays need to be taken into account. In this work, we present an algorithm to find the minimal decoupling buffer sizes for a NoC using TDMA and credit-based end-to-end flow-control, subject to the performance constraints of the applications running on the SoC. Our experiments show that our method results in a 84% reduction of the total NoC buffer area when compared to the state-of-the art buffer-sizing methods. Moreover, our method has a low run-time complexity, producing results in the order of minutes for our experiments, enabling quick design cycles for large SoC designs. Finally, our method can take into account multiple usecases that are running on the same SoC.

Published in:
Proceedings of the International Conference on Hardware/Software Codes and System Synthesis (CODES+ISSS), ISBN:3-9810801-0-6, 118 - 123
Presented at:
International Conference on Hardware/Software Codes and System Synthesis (CODES+ISSS), Seoul, Korea, October 22-25, 2006

 Record created 2006-09-05, last modified 2018-03-17

Download fulltext

Rate this document:

Rate this document:
(Not yet reviewed)