Compiler-Driven Leakage Energy Reduction in Banked Register Files

Tomorrow’s embedded devices need to run high-resolution multimedia applications which need an enormous computational complexity with a very low energy consumption constraint. In this context, the register file is one of the key sources of power consumption and its inappropriate design and management can severely affect the performance of the system. In this paper, we present a new approach to reduce the energy of the shared register file in upcoming embedded VLIW architectures with several processing units. Energy savings up to a 60% can be obtained in the register file without any performance penalty. It is based on a set of hardware extensions and a compiler-based energy-aware reg- ister assignment algorithm that enable the de/activation of parts of the register file (i.e. sub-banks) in an independent way at run-time, which can be easily included in these embedded architectures.

Published in:
Power and Timing Modelling, Optimization and Simulation (PATMOS), 107-116
Presented at:
Power and Timing Modeling, Optimization and Simulation (PATMOS), Montpellier, France, 13-15 September 2006
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 Record created 2006-07-28, last modified 2018-03-18

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