Weak Inversion Performance of CMOS and DCVSPG Logic Families in Sub-300mV Range

In this paper the advantages of using Differential Cascode Voltage Switch Pass Gate (DCVSPG) logic with regard to standard CMOS for subthreshold operation are presented. The two families are compared in terms of their performance and Energy-Delay-Product (EDP) figures. Multiple gates were simulated using 0.18µm standard CMOS technology. Simulation results show that DCVSPG NAND2 gate has 71%, DCVSPG NOR2 gate has 82% and DCVSPG full adder has 66% EDP savings over the CMOS counterparts.


Published in:
Proceedings of the International Symposium on Circuits and Systems, 1251-1254
Presented at:
IEEE International Symposium on Circuits and Systems (ISCAS), Island of Kos, Greece, May 21-25
Year:
2006
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 Record created 2006-07-12, last modified 2018-03-17

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