000088123 001__ 88123
000088123 005__ 20180317092416.0
000088123 02470 $$2ISI$$a000245413503069
000088123 037__ $$aCONF
000088123 245__ $$aVia-Programmable Expanded Universal Logic Gate in MCML for Structured ASIC Applications: Part I - Circuit Design
000088123 269__ $$a2006
000088123 260__ $$c2006
000088123 336__ $$aConference Papers
000088123 520__ $$aThis paper presents a regular layout fabric made of via-programmable MCML universal logic cells for structured ASIC applications and the associated design flow. The proposed structured ASIC fabric offers high speed operation, very high noise immunity, as well as low production cost due to the via-programmable properties of the universal logic cell. Implementations of a number of circuits are presented and the area/speed performances are compared with a CMOS implementation using a commercial  standard cell library in 0.18 um CMOS technology.
000088123 6531_ $$astructured asic
000088123 6531_ $$aprogrammable logic
000088123 6531_ $$adifferential design
000088123 700__ $$aBrauer, Elizabeth
000088123 700__ $$aBadel, Stéphane
000088123 700__ $$aHatirnaz, Ilhan
000088123 700__ $$0240162$$aLeblebici, Yusuf$$g112194
000088123 7112_ $$aIEEE International Symposium on Circuits and Systems (ISCAS)$$cKos, Greece$$dMay 21-24
000088123 773__ $$q2893-2896$$tProceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)
000088123 909CO $$ooai:infoscience.tind.io:88123$$pSTI$$pconf
000088123 909C0 $$0252051$$pLSM$$xU10325
000088123 917Z8 $$x112194
000088123 937__ $$aLSM-CONF-2006-002
000088123 973__ $$aEPFL$$rREVIEWED$$sPUBLISHED
000088123 980__ $$aCONF